1. Field of the Invention
The invention relates in general to a semiconductor memory device having capacitors, and in particular to a dynamic random-access memory (DRAM) semiconductor device. More particularly, the invention relates to the semiconductor structural configuration of a memory cell unit for a DRAM device featuring a transfer transistor and a tree-type storage capacitor, and to the process for fabricating the capacitor.
2. Technical Background
Semiconductor memory devices such as DRAMs include arrays of memory cell units for the storage of digital information in binary form. Each of the DRAM memory cells in the typical device memory array in particular includes a transistor and a capacitor for the storage of one bit of binary data. FIG. 1 of the accompanying drawings is a schematic diagram of such a DRAM memory cell unit. The schematic diagram shows that the typical memory cell includes a transfer transistor T and a storage capacitor C.
The transistor T functions as an electronic switch that transfers the binary data to be stored in or retrieved from the memory in the cell unit of FIG. 1 by connecting the cell to the external data circuitry. The memory cell unit stores the binary data as a logical high or low represented respectively by either a charged or discharged status of the storage capacitor C. To implement this, the source of the transfer transistor T is connected to the bit line BL of the memory array, and the drain thereof to one electrode 6 of the storage capacitor C. The other of the pair of capacitor electrodes, 8, is tied to the ground plane of the entire system. As is well known, the storage dielectric layer 7 directly affects the capacitance of the storage capacitor C. The gate of the transfer transistor T is connected to the word line WL of the memory cell array system, which is controlled to enable charging of the storage capacitor C when the memory cell unit is accessed.
In conventional 1 mega-byte (1 MB) DRAM devices, storage capacitors having a substantially two-dimensional capacitor structural configuration, generally known as a planar-type capacitor, are utilized as the storage capacitors for the memory cell. However, planar-type capacitors take up considerable integrated circuit die surface area, which is a disadvantageous factor constraining the miniaturization of the fabricated memory device. For high-density DRAM devices, 4 MB and greater for example, a planar-type storage capacitor structure becomes unsuitable, since the device fabrication resolution is increased to such a level that the storage capacitor does not have sufficient capacitance to hold enough electric charge for practical DRAM operational needs. Three-dimensional storage capacitor structural configurations would have to be used to increase the capacitor electrode surface area within the limited device die surface area assigned for each of the memory cell units. For this reason, DRAM memory cell storage capacitor structural configurations such as the stacked type or trench type were introduced.
Although stacked or trench type capacitors may have increased capacitance compared with the planar type for comparable assigned device die surface area, they still cannot provide sufficient practical capacitance for DRAM devices featuring even higher storage densities in the range of, for example, 64 MB per device or greater. In other words, simple three-dimensional capacitor structural configurations are no longer sufficient.
One proposed solution for increasing storage capacitor capacitance is the so-called fin-type stacked configuration. For example, Ema et al. proposed one such capacitor structural configuration in the paper "3-dimensional Stacked Capacitor Cell for 16M and 64M DRAMs," International Electron Devices Meeting, pp. 592-595, December 1988. Essentially, a fin-type configuration makes use of a number of stacked layers to increase storage capacitor electrode surface area. Further examples of this fin-type storage capacitor structural configuration are disclosed in U.S Pat. Nos. 5,071,783; 5,126,810; 5,196,365; and 5,206,787.
An additional type of storage capacitor structure for DRAM memory cell unit is the cylindrically-stacked type configuration. Wakamiya et al. described an example of this type of capacitor structure in the paper "Novel Stacked Capacitor Cell for 64-MB DRAM," 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. This is a structure built around a dielectric layer sandwiched between the electrodes, which extends in the form of a vertical cylinder to increase capacitor electrode surface area. U.S. Pat. No. 5,077,688 describes such a capacitor structure.
However, as the level of integration of semiconductor devices continues to increase, DRAM memory cells become ever smaller in dimension. As persons skilled in the art are well aware, storage capacitors sharing smaller surface areas in the semiconductor substrate in which they are fabricated suffer decreased capacitance. One of the direct results is that the DRAM performance characteristics are degraded by an increase in soft error probability, due to .alpha. particle irradiation. Thus, efforts to increase DRAM memory cell storage capacitor capacitance by enlarging the capacitor electrode surface area physically, despite the trend of device miniaturization, remains one of the major problems for fabricating larger DRAM memory devices.